A Sequence is a linear series of events. It is the fundamental reusable block of SVA. Sequences describe "what happens" (e.g., A then B then C) which can then be used in properties.
Use the sequence keyword. Sequences can be declared in modules, interfaces,
programs,
or packages.
sequence s_burst_start;
// req goes high, then 2 cycles later ack is high
req ##2 ack;
endsequenceSequences are like functions—you can pass arguments to them. This makes them highly reusable across different signals in your design.
// Sequence to check if 'sig' holds value 'val' for 'N' cycles
sequence s_hold_value(signal, val, N);
(signal == val) [*N];
endsequence
property p_reset_check;
@(posedge clk) $rose(reset) |-> s_hold_value(enable, 0, 5);
endpropertyYou can combine sequences using logical operators.
seq1 and seq2: Both start at same time. Both must succeed (can end at
different times). Global success is when the last one finishes.seq1 or seq2: At least one must succeed.seq1 intersect seq2: Both must start together AND end together.intersect requires the two sequences to be of equal length
(start and end together). and only requires them to start and succeed,
regardless of length (the composite sequence ends when the longer one ends).