- Non-intrusive: No need to edit the synthesis-ready RTL.
- Modularity: Keep assertions in a separate file (e.g.,
fifo_props.sv). - Reusability: Apply the same assertion module to multiple instances of a design.
Assertion Binding
The bind construct allows you to attach assertions (or any module/interface) to a
Design Unit (module)
without touching the original RTL code. This is crucial for keeping VerificationIP separate from
DesignIP.
Why use Bind?
Bind Syntax
// bind (....);
bind fifo_rtl my_fifo_assertions i_assertions (
.clk(clk),
.rst_n(reset_n),
.data_in(d_in),
.full(fifo_full)
);
In this example, my_fifo_assertions is "instantiated" inside
fifo_rtl as if you had written the instantiation there yourself.
Binding to Instances
You can bind to a specific instance in the hierarchy instead of the module definition (which affects ALL instances).
bind top.u_fifo_0 my_fifo_assertions i_props (...);Common Interview Questions
Q: Can I bind an interface to a module?
Yes! This is a very powerful pattern. You can bind a SystemVerilog Interface to an RTL
module to "spy" on its internal signals, and then pass that virtual interface to your
UVM testbench.