Concurrent assertions are the heart of SystemVerilog Assertions (SVA). Unlike immediate assertions, they describe behavior over time, synchronized to a clock.
Concurrent assertions continuously monitor the design for specific temporal relationships. For example: "If Signal A goes high, Signal B must go high within 3 clock cycles."
Typically, you define a property (the rule) and then assert it.
// 1. Define the Property
property p_req_grant;
@(posedge clk) req |-> ##[1:3] gnt;
endproperty
// 2. Assert the Property
a_req_grant: assert property (p_req_grant)
else $error("Protocol Violation: Grant missing after Request!");SVA relies heavily on Implication Operators to define "Cause and Effect" relationships.
|-> (Overlapping): If the condition (LHS) is true, the consequence (RHS)
starts checking in the same clock cycle.|=> (Non-Overlapping): If the LHS is true, the RHS check starts in the
next clock cycle.// Overlapping: If valid is 1, data must be good NOW
assert property (@(posedge clk) valid |-> !is_x(data));
// Non-overlapping: If req is 1, ack must be 1 NEXT cycle
assert property (@(posedge clk) req |=> ack);|->) assertions only
"fire" when the Left Hand Side (LHS) is true. If the LHS is false (e.g., no Request),
the assertion is not really checked, but the simulator counts it as a "success"
(Vacuous). Real failures happen only when LHS is True AND RHS is False.
@(posedge clk) block.