Immediate Assertions

Immediate assertions are the simplest form of checks in SystemVerilog. They function just like if statements, checking a condition instantaneously at the moment of execution.

Overview

Think of an immediate assertion as a "Sanity Check" embedded in your procedural code. Unlike concurrent assertions, they do not depend on clock cycles or temporal sequences. If the condition evaluates to false, the assertion fails immediately.

They are widely used inside always blocks, tasks, and functions to verify logic correctness (e.g., checking invalid enum values).

Syntax Logic

Basic Syntax
label: assert (condition) 
    pass_statement; // Optional, usually empty
else 
    fail_statement; // Highly Recommended
Note: While the else block is optional, omiting it is bad practice. Without it, the simulator might print a generic "Assertion failed" message, making debug hard.

Practical Example

always_comb begin
    // When Request is high, Grant must eventually be high (simple check)
    // Here we just check static configuration logic
    if (mode == BURST) begin
        // Check that burst_len is valid
        a_burst_cfg: assert (burst_len > 0 && burst_len <= 16)
        else $error("Error: Invalid Burst Length %0d in Burst Mode!", burst_len);
    end
end

Deferred Assertions (assert final)

One major drawback of standard immediate assertions is that they can be "noisy". In a simulation time-step, signals often fluctuate (delta glitches) before settling. A standard assert might fire on a temporary glitch.

Solution: Use assert final. This tells the simulator to "Wait until this time step is finished, then check."

Deferred vs Immediate
always_comb begin
    // Standard: Fires on EVERY glitch in 'cnt'
    a1: assert (cnt < MAX); 

    // Deferred: Checks ONLY the final settled value of 'cnt' in this time step
    a2: assert final (cnt < MAX) else $error("Count overflow detected!");
end

Severity Tasks

  • $fatal: Stops simulation immediately. Use for critical failures.
  • $error: Prints error, continues simulation. (Most common).
  • $warning: Prints warning.
  • $info: Informational message only.

Common Interview Questions

Q: When should I use an immediate assertion vs a concurrent assertion?
Use Immediate Assertions for checks that have no time element and occur inside procedural code (e.g., checking variable values inside a function). Use Concurrent Assertions for verifying protocol behavior that spans across clock cycles (e.g., "Acknowledge must follow Request within 3 cycles").
Q: What is a deferred assertion?
A deferred assertion (`assert final`) is an immediate assertion that waits for the "Postponed" region of the simulation time slot to execute. This avoids reporting false failures caused by temporary glitches (delta-cycle hazards) in combinatorial logic.