Assertions aren't just for finding bugs (Red Checks). They can also be used to confirm that interesting scenarios actually occurred during simulation (Green Checks). This is called Assertion-Based Coverage.
To track how many times a property was satisfied, use the cover property
statement
instead of assert property.
// Count how many times we had a burst of 4 items
property p_burst_4;
@(posedge clk) $rose(req) |-> ack [*4];
endproperty
c_burst_4: cover property (p_burst_4);| Keyword | Purpose | Failure Action |
|---|---|---|
assert |
Verify correctness (Catch Bugs) | Error / Fatal |
cover |
Analyze behavior (Gather Stats) | None (Just doesn't count) |
assume |
Constrain inputs (Formal Verification) | Error if input violates |
You have now covered the essentials of SystemVerilog Assertions! From basic immediate checks to complex temporal sequences and coverage.