In modern UVM verification environments, we rarely use clock-based events directly in the
covergroup definition.
Instead, we define the covergroup with no arguments and call .sample() inside
the Monitor component.
// 1. Define without event
covergroup cg_packet;
cp_len: coverpoint pkt.len;
endgroup
// 2. Instantiate
cg_packet cg = new();
// 3. Sample procedurally
task run_phase;
forever begin
@(posedge vif.clk);
if (vif.valid_out) begin
// Capture data into packet object
pkt.len = vif.data_len;
// TRIGGGER COVERAGE NOW
bg.sample();
end
end
endtask