A coverpoint tells SystemVerilog exactly "what" to track. It can be a simple signal, a complex expression, or even a function return value.
Inside a covergroup, you declare coverpoints using the coverpoint keyword.
You can (and should) give them a label for easier debugging.
covergroup cg @(posedge clk);
// Unlabeled coverpoint (hard to debug)
coverpoint simple_sig;
// Labeled coverpoint (Recommended)
cp_state: coverpoint state_machine_reg;
// Covering an expression
cp_sum: coverpoint (a + b);
endgroup
Sometimes you only want to collect coverage under certain conditions (e.g., only when reset
is not active).
Use the iff keyword.
covergroup cg_bus @(posedge clk);
// Only sample 'data' coverage when 'valid' is high
// AND reset is not active.
cp_data: coverpoint data iff (valid && !rst_n);
endgroupThe iff condition works as a gating mechanism. If the condition is false,
the coverpoint is completely ignored for that sample event.
If you do not define explicit bins inside a coverpoint, SystemVerilog will
automatically create bins for you.
If the signal width is small (e.g., 2 bits), it creates a bin for every value. If it's large
(e.g., 32 bits), it creates a default of 64 bins (configurable via options).
auto_bin_max) unless you specify explicit bins.