Finite State Machines (FSM)

• Moore Machine: Output depends ONLY on the current state. Output is stable for the entire clock cycle. Safer but may be slower (more latency).
• Mealy Machine: Output depends on the current state AND current inputs. Output reacts immediately to input changes (combinational path). Less latency but improved risk of glitches.

• Binary (00, 01, 10, 11): Uses fewer flip-flops (log2(N)). Requires more complex combinational decoding logic. Good for small FSMs or area-constrained designs.
• One-Hot (0001, 0010, 0100, 1000): Uses more flip-flops (N). Decoding is simple/fast (just check one bit). Preferred for high-speed FSMs (FPGA/ASIC) as flip-flops are cheap but logic depth matters.

A glitch is a temporary unwanted signal transition.

In Mealy machines, since outputs depend directly on inputs, any noise or skew on the input lines can propagate directly to the output asynchronously, causing a glitch.

Solution: Register the outputs of the FSM (making it effectively a Moore machine at the boundary) to filter out glitches.

A safe FSM ensures that if the state machine enters an illegal state (e.g. 101 when only 4 states 0-3 are defined), it can recover.

Always include a default clause in your CASE statement that resets the state to IDLE.