Clocks & Resets Questions

• Synchronous: Sampled only on the active edge of the clock. If the clock dies, reset doesn't work. Good for glitch filtering.
• Asynchronous: Affects Q output immediately, regardless of clock. Must be de-asserted synchronously to avoid metastability (Recovery/Removal check).

Divide by 2: Simple toggle flip-flop.

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) div2 <= 0;
    else        div2 <= ~div2;
end

Divide by 3 (50% Duty Cycle): Requires two bits and using both posedge and negedge clocks, then OR-ing the outputs.