A transfer occurs ONLY when both VALID and READY are High on the same rising clock edge.
- Source (Master or Slave): Asserts
VALIDwhen data/control is available. - Destination (Slave or Master): Asserts
READYwhen it can accept the information.
The AXI Handshake
The core mechanism of flow control in AXI. Every channel uses the VALID/READY handshake to transfer information.
The Golden Rule
Assertion Rules
Critical Restriction
Once VALID is asserted, it MUST remain asserted until the handshake occurs
(Ready comes High). The Source CANNOT deassert VALID just because Ready is Low.
However, READY can toggle. The Destination can assert Ready before Valid
arrives, or wait for Valid to arrive.
Deadlock Prevention
To prevent deadlocks, the Protocol specifies dependency rules:
- VALID cannot depend on READY: A Source must not wait for Ready to be High before asserting Valid.
- READY can depend on VALID: A Destination IS allowed to wait for Valid before asserting Ready (though asserting Ready early is better for performance).
// GOOD:
assign VALID = data_available; // Purely internal logic
assign READY = buffer_not_full;
// BAD (Deadlock Risk):
assign VALID = data_available && READY; // Depends on Ready!Common Interview Questions
Q: Can the Master wait for AWREADY before asserting AWVALID?
No. This is a protocol violation. The Master must be able to assert AWVALID solely based
on its own availability of an address. If it waits for READY, and the Slave is waiting
for VALID (which it is allowed to do), the system will deadlock.