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The 5 Channels of AXI

AXI splits the protocol into 5 independent channels. This architecture allows specific performance optimizations like out-of-order execution and simultaneous read/write.

Channel Architecture

Unlike AHB which shares buses for Read/Write, AXI has dedicated channels. A Read and a Write can happen at the exact same time. 

Write Channels:
1. Write Address Channel (AW) -> Master sends Address & Control
2. Write Data Channel    (W)  -> Master sends Data
3. Write Response Channel(B)  -> Slave sends Status (OKAY/SLVERR)

Read Channels:
4. Read Address Channel  (AR) -> Master sends Address & Control
5. Read Data Channel     (R)  -> Slave sends Data & Status

1. Write Address Channel (AW)

Prefix: AW. Carries the destination address and transaction control information.

  • AWADDR: Target address.
  • AWLEN: Number of transfers in burst.
  • AWSIZE: Size of each transfer.
  • AWBURST: Burst type (Fixed, Incr, Wrap).
  • AWID: Transaction ID (for out-of-order).
  • AWVALID / AWREADY: Handshake.

2. Write Data Channel (W)

Prefix: W. Carries the write data.

  • WDATA: The data payload.
  • WSTRB: Write strobes (byte enables).
  • WLAST: Indicates the last beat of the burst.
  • WVALID / WREADY: Handshake.

Note

WID was removed in AXI4. Write data is assumed to be in order with Write Addresses from the same Master.

3. Write Response Channel (B)

Prefix: B. Confirms completion of the write transaction. Sent by Slave.

  • BRESP: Status (OKAY, EXOKAY, SLVERR, DECERR).
  • BID: Matches the AWID of the transaction being acknowledged.
  • BVALID / BREADY: Handshake.

Common Interview Questions

Q: Why does the Write Response channel exist?
In buffered writes, the Master needs to know when the data actually reached the destination safely. The 'B' channel provides this acknowledgment *after* the entire burst is received.
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