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Write Transfers

How data is written to a peripheral using the Setup and Access phases.

Basic Write (No Wait States)

A write transfer completes in 2 clock cycles if the Slave is ready immediately.

        T1 (SETUP)      T2 (ACCESS)     T3 (DONE/IDLE)
PCLK   : __/``\_______/``\_______/``\__
PADDR  :   < A >          < A >           < - >
PWRITE :   < 1 >          < 1 >           < - >
PSEL   : __/``````````````````````\____
PENABLE: _____________ /``````````\____
PWDATA :   < D >          < D >           < - >
PREADY : ------------- 1 -------------
        ^              ^              ^
     Start Setup    Start Access    Sample Ready (Done)

Write with Wait States

If PREADY is LOW during the Access phase, the Master must hold all signals stable until PREADY goes HIGH. 

        T1        T2 (Wait)   T3 (Done)
PCLK   : __/``\__/``\_______/``\__
PSEL   :   HIGH      HIGH       LOW
PENABLE:   LOW       HIGH       LOW  (Stays HIGH!)
PREADY : -------- 0 ---------- 1 --
PADDR  :   < A >     < A >
PWDATA :   < D >     < D >

// T2: Access phase starts. PREADY is 0.
// Master detects PREADY=0. It MUST NOT deassert PENABLE or change Data.
// T3: PREADY is 1. Transfer completes.

SVA Check for Write Stability

Ensuring data doesn't change during wait states.

property p_write_stable;
    @(posedge pclk) disable iff (!presetn)
    (psel && penable && !pready && pwrite) |-> 
    ($stable(pwdata) && $stable(paddr) && $stable(pwrite));
endproperty

assert property(p_write_stable);
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