| Signal | Source | Description |
|---|---|---|
PCLK |
Clock Source | Bus clock. All transfers are synchronized to the rising edge. |
PRESETn |
Reset Controller | Active LOW system reset. |
APB Signals Reference
The Advanced Peripheral Bus (APB) is defined by a small, simple set of signals. It is low-cost and low-power, optimized for minimal interface complexity.
System Signals
Address and Control (Master -> Slave)
| Signal | Width | Description |
|---|---|---|
PADDR |
32 | Address Bus. |
PSELx |
1 | Slave Select. There is one PSEL signal for each Slave in the system (PSEL1, PSEL2...). Indicates that the slave is targeted. |
PENABLE |
1 | Enable. Indicates the second and subsequent cycles of an APB transfer. |
PWRITE |
1 | Direction. HIGH = Write, LOW = Read. |
PWDATA |
32 | Write Data. |
PPROT |
3 | Protection (Added in APB4). [0]: Normal/Privileged, [1]: Secure/Non-secure, [2]: Data/Instruction. |
PSTRB |
4 | Write Strobe (Added in APB4). Indicates which byte lanes are active. |
Response Signals (Slave -> Master)
| Signal | Width | Description |
|---|---|---|
PREADY |
1 | Ready. Used to extend the transfer (Wait states). If LOW, PENABLE remains HIGH. |
PRDATA |
32 | Read Data. |
PSLVERR |
1 | Slave Error (Added in APB3). Indicates a transfer failed. |
Common Interview Questions
Q: What is the difference between PSEL and PENABLE?
PSEL indicates the "Setup Phase" (Cycle T1). PENABLE goes HIGH
in the following cycle ("Access Phase", T2). PSEL asserts first, effectively warning the
slave, then PENABLE asserts to actually execute the command.