UVM Monitor

The eyes and ears of the testbench. It passively observes signals and converts them into transactions.

Passive Observation

The monitor NEVER drives signals (it only reads them). It converts signal activity into uvm_sequence_item objects and broadcasts them via an analysis_port.

class my_monitor extends uvm_monitor;
    `uvm_component_utils(my_monitor)
    virtual my_if vif;
    uvm_analysis_port #(my_transaction) mon_ap; // Broadcaster

    function new(string name, uvm_component parent);
        super.new(name, parent);
        mon_ap = new("mon_ap", this);
    endfunction

    task run_phase(uvm_phase phase);
        forever begin
            @(posedge vif.clk);
            if(vif.valid) begin
                my_transaction tr = my_transaction::type_id::create("tr");
                tr.data = vif.data;
                tr.addr = vif.addr;
                mon_ap.write(tr); // Publish to Scoreboard/Coverage
            end
        end
    endtask
endclass

Differences: Driver vs Monitor

  • Driver: Active (Drives signals), Connected to Sequencer (Pull), 1 per interface.
  • Monitor: Passive (Samples signals), Connected to Subscribers (Push), Can have multiple (e.g., Bus monitor, Protocol monitor).