Home › SystemVerilog › Interface Basics

Interface Basics in SystemVerilog

Interfaces bundle related signals together, making connections cleaner and reducing errors. Instead of connecting 20 individual wires, you connect one interface. Let's understand how interfaces work and why they're essential for verification.

Why Use Interfaces?

In traditional Verilog, connecting modules requires listing every signal individually. For a complex bus like AXI with 50+ signals, this becomes tedious and error-prone.

Think of interfaces like a multi-pin connector. Instead of connecting 20 individual wires (easy to mix up!), you use one connector that bundles all wires together. USB cables work this way - one connector, multiple signals inside.

Problems Interfaces Solve

  • Reduce port lists - One interface vs dozens of signals
  • Prevent connection errors - Can't swap signals by mistake
  • Enable reuse - Same interface for multiple modules
  • Simplify changes - Add a signal once, available everywhere
  • Support verification - Essential for UVM testbenches

Defining an Interface

An interface is defined similarly to a module, but it groups signals rather than logic. It can also include clocking blocks, modports, and even tasks and functions.

Simple Interface Definition
interface simple_bus_if;
    // Signals
    logic        clk;
    logic        reset;
    logic [31:0] addr;
    logic [31:0] data;
    logic        valid;
    logic        ready;
    logic        write;
endinterface
Interface with Parameters
interface bus_if #(
    parameter ADDR_WIDTH = 32,
    parameter DATA_WIDTH = 32
);
    logic                    clk;
    logic                    rst_n;
    logic [ADDR_WIDTH-1:0]   addr;
    logic [DATA_WIDTH-1:0]   wdata;
    logic [DATA_WIDTH-1:0]   rdata;
    logic                    write;
    logic                    valid;
    logic                    ready;
endinterface

Interface vs Module

Interfaces contain signals and optional logic. Modules contain actual design logic. In the testbench, the interface acts as a "contract" between components.

Using Interfaces

Instantiating an Interface

Interface Instantiation
// In the top-level testbench
module tb_top;
    // Instantiate the interface
    bus_if bus();  // Like instantiating a module
    
    // Connect clock
    initial begin
        bus.clk = 0;
        forever #5 bus.clk = ~bus.clk;
    end
    
    // Connect reset
    initial begin
        bus.rst_n = 0;
        #20 bus.rst_n = 1;
    end
    
    // Instantiate DUT with interface
    dut u_dut (
        .clk   (bus.clk),
        .rst_n (bus.rst_n),
        .addr  (bus.addr),
        .wdata (bus.wdata),
        .rdata (bus.rdata),
        .write (bus.write),
        .valid (bus.valid),
        .ready (bus.ready)
    );
endmodule

Accessing Interface Signals

Signal Access
// Access signals using dot notation
bus.addr  = 32'h1000;
bus.wdata = 32'hDEADBEEF;
bus.write = 1;
bus.valid = 1;

// Wait for ready
@(posedge bus.clk);
while (!bus.ready) @(posedge bus.clk);

// Read rdata
$display("Read data: 0x%h", bus.rdata);

Connecting Modules with Interfaces

Modules can accept an interface as a port. This dramatically simplifies port lists.

Module with Interface Port
// DUT with interface port
module memory_controller (
    bus_if bus  // Interface as port!
);
    // Access signals through the interface
    always @(posedge bus.clk) begin
        if (!bus.rst_n) begin
            bus.ready <= 0;
        end else if (bus.valid) begin
            if (bus.write) begin
                // Write operation
                mem[bus.addr] <= bus.wdata;
            end else begin
                // Read operation
                bus.rdata <= mem[bus.addr];
            end
            bus.ready <= 1;
        end else begin
            bus.ready <= 0;
        end
    end
endmodule

Clean Connections!

Notice how the module only has one port instead of 8+ individual signals. When you need to add a new signal, just add it to the interface - no need to update every module's port list.

Interface with Clocking Block

Clocking blocks define when signals are sampled and driven. This prevents race conditions between testbench and DUT.

Interface with Clocking Block
interface bus_if (input logic clk);
    logic        rst_n;
    logic [31:0] addr;
    logic [31:0] wdata;
    logic [31:0] rdata;
    logic        write;
    logic        valid;
    logic        ready;
    
    // Clocking block for testbench
    clocking driver_cb @(posedge clk);
        default input #1step output #0;
        output addr, wdata, write, valid;
        input  rdata, ready;
    endclocking
    
    // Clocking block for monitor
    clocking monitor_cb @(posedge clk);
        default input #1step;
        input addr, wdata, rdata, write, valid, ready;
    endclocking
endinterface

Input vs Output in Clocking Blocks

input means the testbench reads this signal. output means the testbench drives this signal. It's from the testbench's perspective, not the DUT's!

Quick Summary

  • Interface - Bundles related signals together
  • Definition - Similar to module but for signals
  • Parameters - Make interfaces configurable
  • Clocking blocks - Define sampling/driving timing
  • Use interfaces to simplify port connections
  • Essential for UVM testbenches

What's Next?

Continue learning about interfaces:

Previous Inline Constraints Next Modports