Basic Read & Write Transfers

The simplest AHB transfer consists of an Address Phase and a Data Phase. Even without bursts or pipelining, understanding this fundamental unit is key.

The Two Phases

Every AHB transfer requires at least two clock cycles to complete:

Address Phase (Cycle N): The Master drives address and control signals (HADDR, HWRITE, HTRANS).
Data Phase (Cycle N+1): The data is sampled (HWDATA) or driven (HRDATA).

Important

Because of pipelining, the Data Phase of Transfer A happens at the same time as the Address Phase of Transfer B.

Simple Write Transfer

A zero-wait-state write.

CLK     : __/``\__/``\__/``\__  
HADDR   :   < A > < B > < - >   // A is driven at T0
HTRANS  :   < N > < I > < I >   // Non-Seq
HWRITE  :   < 1 > < 0 > < 0 >   // Write=1
HWDATA  :   < - > < D > < - >   // Data D driven at T1
HREADY  : ----1-------1-------  // Slave is ready instantly

// T0: Master drives HADDR=A, HTRANS=NONSEQ, HWRITE=1
// T1: Master drives HWDATA=D. Slave samples A and Ctrl.
// T1 (end): Slave samples HWDATA (if HREADY=1).

Simple Read Transfer

A zero-wait-state read.

CLK     : __/``\__/``\__/``\__
HADDR   :   < A > < - >         // Address A driven at T0
HWRITE  :   < 0 > < - >         // Read=0
HTRANS  :   < N > < I >
HRDATA  :   < - > < D >         // Slave drives Data D at T1

Wait States (HREADY)

If the Slave needs more time (e.g., memory access latency), it pulls HREADY LOW during the Data Phase. The Master must extend the Data Phase until HREADY goes HIGH.

CLK     : __/``\__/``\__/``\__/``\__
HADDR   :   < A > < B > < B > < C >  // Addr B held for 2 cycles
HTRANS  :   < N > < N > < N > < I >  // Trans B held
HREADY  : ----1-------0-------1----- // Slave busy at T1
DATA    :   < A > < - > < B > < C >  // Data B sampled at T2

// Transfer A completes at T1.
// Transfer B starts Addr Phase at T1... 
// Slave pulls HREADY=0 at T1.
// Master sees HREADY=0, so it MUST HOLD Addr B and Trans B at T2.
// Slave releases HREADY=1 at T2.
// Transfer B completes Data Phase at T3.

Common Interview Questions

Q: Who drives the HREADY signal?

The Slave drives HREADYOUT to indicate it is ready. The Mux/Arbiter combines all slave ready signals into a system-wide HREADY which is fed back to the Master and all Slaves.

Q: When is HWDATA valid?

HWDATA is valid during the Data Phase (one cycle after the Address Phase). It must be stable until HREADY is HIGH at the rising edge of HCLK.

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